Heartbleed exposes weaknesses in hardware design
By Agam Shah, IDG News Service | August 15th, 2014
Heartbleed highlights memory and cache architecture weaknesses, but a DHS-funded project proposes changes.
Heartbleed may have been a software bug, but it highlighted glaring weaknesses in existing hardware architectures, which remain vulnerable to memory-bound attacks, a university researcher said this week.
Data is vulnerable to hackers when in transit or in computer memory, said Ruby Lee, professor of engineering at Princeton University’s Department of Electrical Engineering, at a presentation to the Hot Chips conference.
The weakness is in the memory and cache, or secondary memory where data temporarily resides before being sent for processing or storage.
“This is correctly functioning hardware — with no bugs — but it is leaking out information,” said Lee, who was chief architect and one of the lead processor developers at Hewlett-Packard before joining Princeton.
Securing memory was a hot discussion topic among chip experts at the forum, and Heartbleed sparked discussions on how hackers could access data from memory, storage and interconnects. Chip makers talked about hardware being the first line of defense against such attacks, and proposed techniques to scramble data and secure keys within a chip. A research project at Princeton funded by the U.S. Department of Homeland Security recommended a new architecture that could secure memory and cache.
Heartbleed exposed a critical defect in affected versions of the OpenSSL software library, which enables secure communication over the Internet and networks. Heartbleed affected servers, networking gear and appliances, and hardware makers have since issued patches to protect systems.
Heartbleed was a “side-channel” attack that determined the availability of systems, and hackers could take advantage of defects in OpenSSL to read cache. It would be possible for attackers to steal important data such as passwords, private keys and other identify information from memory and cache, Lee said.
“Lots of people have talked about the attacks, but very few people have talked about the solutions,” Lee said. “The hardware is still leaking out your secret keys all the time. Every single piece of hardware that has a cache is vulnerable to cache-side channel leakage.”
The weak link is the fixed memory addresses of cache. Attackers can effectively re-create the use of cache by a victim and map bits of keys to specific parts of memory used. Attackers can then extract data from the tracked memory addresses to reconstruct keys.
“Because there’s a fixed memory address … the attacker can look backwards and figure out which memory addresses the victim used,” Lee said. “Then he can devise the whole key.”
Attackers will be able to “read out the crown jewel of primary keys — the symmetric keys used for encryption and the private keys that are used for identity in the digital world that you should protect,” Lee said.
It’s difficult to launch software attacks on hardware, but side-channel attacks can be dangerous, Lee said. An exposed system could be left vulnerable by other bugs like Heartbleed.
“If the attacker can attack fixed systems, it’s easier. Once he finds a path, he can attack 80 percent of the system and … when he comes back, he can find the same path in,” Lee said.
To mitigate such attacks, Lee and researchers at Princeton have reconstructed cache architecture so tracks left by the victim are effectively wiped out, making it difficult to carry out side-channel attacks. The cache architecture, called Newcache, could replace the exposed cache and memory in systems today.
“[DHS] would very much like the industry to adopt some of these techniques,” Lee said.
Newcache is structured like regular cache, but has dynamic and randomized cache mapping that will make it harder for attackers to correlate memory usage to key bits. That will make it hard for hackers to map the cache and extract data.
“You want to be a moving target so that the attacker … can’t get in the next hour or in an identically configured system,” Lee said.
Newcache is ready to implement, and the additional security measures won’t hurt performance, Lee said. Memory typically slows down when new features — like ECC for error correction — are added. But benchmarks of Newcache actually showed improvements in system performance, Lee said.
“The secure caches are much bigger, they aren’t any more power hungry, and with clever circuit design, aren’t any slower than your conventional caches,” Lee said.
It could take years for chip and system makers to change memory features, but Lee said chip makers need to start thinking about securing data within systems, Lee said.
Memory security should be a priority, Newcache or not, Lee said.
“Most of the security is done in a reactive mode. When an attack happens, people scramble to find a defense and close up a hole,” Lee said. “You’ve got to think ahead.”